Hi Hassan, I think I wasn’t clear. I am using either DDR or HBM at a time (not both at the same time), but the channel interleaving isn’t working for any of them.
Regards Yasir From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of hassan yamin Sent: 20 March 2019 15:06 To: gem5 users mailing list <gem5-users@gem5.org> Subject: Re: [gem5-users] Problem with Multiple Channels and Channel Interleaving I think you can only use one type of memory. Memory hash interleaving is mostly for channel selection. Hassan On Wed, 20 Mar 2019, 13:41 Qureshi Yasir Mahmood, <yasir.qure...@epfl.ch<mailto:yasir.qure...@epfl.ch>> wrote: Hi, I am trying to use multiple channels in an ARM FS simulation with both DDR4 and HBM memory models. I use --mem-channels=8 and --mem-size=4GB options to configure the memory size and number of channels. In config.ini I do see 8 memory controllers being initialized (0 to 7), but the memory traffic always goes to just one memory controller, i.e. mem_ctrls7. I enabled the AddrRanges debug flag, and it shows that the ranges were allocated correctly 0: system.membus: Adding range [0x80000000 : 0x17fffffff], [9 : 7] XOR [22 : 19] = 0 for id 6 0: system.membus: Received range change from slave port system.mem_ctrls1.port 0: system.membus: Adding range [0x80000000 : 0x17fffffff], [9 : 7] XOR [21 : 19] = 1 for id 7 0: system.membus: Received range change from slave port system.mem_ctrls2.port 0: system.membus: Adding range [0x80000000 : 0x17fffffff], [9 : 7] XOR [21 : 19] = 2 for id 8 0: system.membus: Received range change from slave port system.mem_ctrls3.port 0: system.membus: Adding range [0x80000000 : 0x17fffffff], [9 : 7] XOR [21 : 19] = 3 for id 9 0: system.membus: Received range change from slave port system.mem_ctrls4.port 0: system.membus: Adding range [0x80000000 : 0x17fffffff], [9 : 7] XOR [21 : 19] = 4 for id 10 0: system.membus: Received range change from slave port system.mem_ctrls5.port 0: system.membus: Adding range [0x80000000 : 0x17fffffff], [9 : 7] XOR [21 : 19] = 5 for id 11 0: system.membus: Received range change from slave port system.mem_ctrls6.port 0: system.membus: Adding range [0x80000000 : 0x17fffffff], [9 : 7] XOR [21 : 19] = 6 for id 12 0: system.membus: Received range change from slave port system.mem_ctrls7.port 0: system.membus: Adding range [0x80000000 : 0x17fffffff], [9 : 7] XOR [21 : 19] = 7 for id 13 . . . 0: system.membus: -- Merging range from 8 ranges 0: system.membus: -- Adding merged range [0x80000000 : 0x17fffffff] I have tried to turn off the XOR hashed interleaving, but it did not help either. I have used both STREAM and also mmap on /dev/mem to allocate memory on selected physical addresses, to be sure what address I am accessing, but the accesses always end up in mem_ctrls7. Can anyone help identify where the problem is ? Is it a problem in the coherent Xbar, which is the being used as the system bus ? Regards Yasir _______________________________________________ gem5-users mailing list gem5-users@gem5.org<mailto:gem5-users@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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