Hi Nikos, Thank you for the reply. I am an older version (Aug 2018) and all the traffic is indeed being routed to a single controller instead of all.
I just checked and see your fix in the commit '34b16aa -- base: Fix isSubset() for addr ranges with interleaving' . I have applied the fix and the interleaving works perfectly fine now with the traffic being routed to all dram controllers now. Thanks a lot. Regards Yasir -----Original Message----- From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Nikos Nikoleris Sent: 20 March 2019 17:36 To: gem5 users mailing list <gem5-users@gem5.org> Subject: Re: [gem5-users] Problem with Multiple Channels and Channel Interleaving Hi Yasir, Are you on a reasonably recent version of gem5? A couple of months back there was a bug in the address map that would essentially route all traffic to a single memory controller. Can you check stats.txt and verify that all dram ctrls are used? Nikos On 20/03/2019 15:14, Qureshi Yasir Mahmood wrote: > Hi Hassan, > > I have done sanity check on that (configs/common/Memconfig.py file), > and it is not the case. As I explicitly allocate and access to > specific memory locations, I expect it to be accesses in a specific > channel, but all the memory accesses go to just one channel. > > Regards > > Yasir > > *From:*gem5-users [mailto:gem5-users-boun...@gem5.org] *On Behalf Of > *hassan yamin > *Sent:* 20 March 2019 15:25 > *To:* gem5 users mailing list <gem5-users@gem5.org> > *Subject:* Re: [gem5-users] Problem with Multiple Channels and Channel > Interleaving > > It means the address bit being used for channel selection is near to > MSB and doesn't change. There is some python file for configuration > where you can select the bit used for channel selection. > > On Wed, 20 Mar 2019, 15:09 Qureshi Yasir Mahmood, > <yasir.qure...@epfl.ch <mailto:yasir.qure...@epfl.ch>> wrote: > > Hi Hassan, > > I think I wasn’t clear. I am using either DDR or HBM at a time (not > both at the same time), but the channel interleaving isn’t working > for any of them. > > Regards > > Yasir > > *From:*gem5-users [mailto:gem5-users-boun...@gem5.org > <mailto:gem5-users-boun...@gem5.org>] *On Behalf Of *hassan yamin > *Sent:* 20 March 2019 15:06 > *To:* gem5 users mailing list <gem5-users@gem5.org > <mailto:gem5-users@gem5.org>> > *Subject:* Re: [gem5-users] Problem with Multiple Channels and > Channel Interleaving > > I think you can only use one type of memory. Memory hash > interleaving is mostly for channel selection. > > Hassan > > On Wed, 20 Mar 2019, 13:41 Qureshi Yasir Mahmood, > <yasir.qure...@epfl.ch <mailto:yasir.qure...@epfl.ch>> wrote: > > Hi, > > I am trying to use multiple channels in an ARM FS simulation > with both DDR4 and HBM memory models. I use --mem-channels=8 and > --mem-size=4GB options to configure the memory size and number > of channels. > > In config.ini I do see 8 memory controllers being initialized (0 > to 7), but the memory traffic always goes to just one memory > controller, i.e. mem_ctrls7. > > I enabled the /AddrRanges/ debug flag, and it shows that the > ranges were allocated correctly > > 0: system.membus: Adding range [0x80000000 : > 0x17fffffff], [9 : 7] XOR [22 : 19] = 0 for id 6 > > 0: system.membus: Received range change from slave port > system.mem_ctrls1.port > > 0: system.membus: Adding range [0x80000000 : > 0x17fffffff], [9 : 7] XOR [21 : 19] = 1 for id 7 > > 0: system.membus: Received range change from slave port > system.mem_ctrls2.port > > 0: system.membus: Adding range [0x80000000 : > 0x17fffffff], [9 : 7] XOR [21 : 19] = 2 for id 8 > > 0: system.membus: Received range change from slave port > system.mem_ctrls3.port > > 0: system.membus: Adding range [0x80000000 : > 0x17fffffff], [9 : 7] XOR [21 : 19] = 3 for id 9 > > 0: system.membus: Received range change from slave port > system.mem_ctrls4.port > > 0: system.membus: Adding range [0x80000000 : > 0x17fffffff], [9 : 7] XOR [21 : 19] = 4 for id 10 > > 0: system.membus: Received range change from slave port > system.mem_ctrls5.port > > 0: system.membus: Adding range [0x80000000 : > 0x17fffffff], [9 : 7] XOR [21 : 19] = 5 for id 11 > > 0: system.membus: Received range change from slave port > system.mem_ctrls6.port > > 0: system.membus: Adding range [0x80000000 : > 0x17fffffff], [9 : 7] XOR [21 : 19] = 6 for id 12 > > 0: system.membus: Received range change from slave port > system.mem_ctrls7.port > > 0: system.membus: Adding range [0x80000000 : > 0x17fffffff], [9 : 7] XOR [21 : 19] = 7 for id 13 > > . > > . > > . > > 0: system.membus: -- Merging range from 8 ranges > > 0: system.membus: -- Adding merged range [0x80000000 : > 0x17fffffff] > > I have tried to turn off the XOR hashed interleaving, but it did > not help either. I have used both STREAM and also mmap on > /dev/mem to allocate memory on selected physical addresses, to > be sure what address I am accessing, but the accesses always end > up in mem_ctrls7. > > Can anyone help identify where the problem is ? Is it a problem > in the coherent Xbar, which is the being used as the system bus ? > > Regards > > Yasir > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org <mailto:gem5-users@gem5.org> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org <mailto:gem5-users@gem5.org> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. 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