Hello, I am relatively new in gem5 simulator, i have to design a multiprocessor architecture with two levels of caches composed of:
- At level 1: the usual L1i and L1d caches - At level 2 (shared by all processors): L2i and L2d caches, L2i inclusive with L1i, and L2d non-inclusive with L1d. What is the best solution? Use *Ruby *and* Slicc*, or just *Python* and *C++*. How should I proceed in this case? I ask this question because the *System* object in gem5 seems to only accept an L2 bus. Thank you in advance. -- *JEATSA TOULEPI Armel* Étudiant En Génie Informatique Tel: +237 650771894 / 655296800
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