Hello all, I am inspecting the code for the basic cache interface, and have come across something I find peculiar. The cache consists of cache blocks equal to the number of sets and ways of the cache. Whenever a block is filled, its whenReady value is set based on the fill_latency value of the cache (currently defined as the data_latency, instead of having its own parameter), along with other parameters. whenReady defines the latency of the next cache access to the aforementioned block, if it is accessed before the block fill operation completes.
However, it seems that this does not accurately capture the effect of filling the cache line. At a very basic level, without any hardware modifications, no cache line should be accessible while the cache line is being filled, as the bitlines will be busy filling the cache line. At the very least, cache blocks of different ways that share the same set should not be accessible until the current tick surpasses the whenReady value for all blocks of the set, considering that these blocks share the same wordline. Are the assumptions made here correct? Second question, is whenReady updated when writes come from the CPU side, or only from the memory side? I can only find evidence from the memory side. Thanks for the help, William Simon
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