Hi everyone,
This might not be a big of a challenge, but I am quite confuse on how to
get it done.
I basically want to create a TCM type of memory which is defined as follows:

               SimpleMemory
                  ^
                   |
CPU -->Non-coherentBus-->non-coherent-cache-->memory

with regard to this architecture, I would like the CPU to first access(get
the data)the SimpeMemory then look for the data in the caches.
How would I achieve or configure this? and also to do this should I do
something with regard to the Memory Address Range?

thanks,




On Fri, 27 Dec 2019 at 17:30, Muhammad Aamir <[email protected]>
wrote:

> Hi everyone,
> This might not be a big of a challenge, but I am quite confuse on how to
> get it done.
> I basically want to create a TCM type of memory which is defined as
> follows:
>
>                SimpleMemory
>                   ^
>                    |
> CPU -->Non-coherentBus-->non-coherent-cache-->memory
>
> with regard to this architecture, I would like the CPU
>
>
>
>
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Reply via email to