Dear all, I noticed that in ARM multi core fs simulation, SPI (shared processor interrupts, Ethernet interrupt for instance) is all handled by cpu0. I was looking for mechanisms letting all cpu involved in handling interrupts.
After some literature research and code digging, seems like 1-N (in gic v2) or 1 of N (in gic v3) features is not supported. Am I missing something here or is this actually some features that are not supported now? Any help is appreciated! Thanks. Best, Heng _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
