Hi Heng,

Even if we don't support 1 to N model in gem5, it is not strictly true that all 
SPIs are handled by cpu0.
In fact this is managed at software level.

SPIs are handled at the Distributor level (GICD): All SPIs (from 32 to 1019) 
have a personal GICD_IROUTER
register selecting to which the PE (cpu) the interrupt will be routed by the 
GIC.

https://developer.arm.com/docs/ddi0601/b/external-system-registers/gicd_irouterne

The register has a set of fields (Affinity numbers) tagging a PE in your 
cluster configuration.
In gem5 core0 will have an affinity value of 0.0.0.0; core1 will have 0.0.0.1
(Anyway have a look at the MPIDR register value in the arm reference manual for 
more info)

So if you want to deliver an interrupt to core1 you should write 0.0.0.1 to the 
specific GICD_IROUTER register.

How can you do that?

I have never tested it, but I think this is doable via the procfs:

Change the value of:

/proc/irq/<irq>/smp_affinity

and double check if this constitutes a write to IROUTER.
Then test the interrupt and let us know if it worked.

if you read /proc/interrupts, it should tell you to which CPU an interrupt has 
been delivered

Regards

Giacomo










________________________________
From: gem5-users <gem5-users-boun...@gem5.org> on behalf of HENG ZHUO 
<hzh...@wisc.edu>
Sent: 25 February 2020 21:15
To: gem5-users@gem5.org <gem5-users@gem5.org>
Subject: [gem5-users] ARM SPI interrupt 1 to N model support

Dear all,

I noticed that in ARM multi core fs simulation, SPI (shared processor 
interrupts, Ethernet interrupt for instance) is all handled by cpu0. I was 
looking for mechanisms letting all cpu involved in handling interrupts.

After some literature research and code digging, seems like 1-N (in gic v2) or 
1 of N (in gic v3) features is not supported. Am I missing something here or is 
this actually some features that are not supported now?

Any help is appreciated! Thanks.

Best,
Heng

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