> The microcode ISA I used I got mostly from an AMD patent from the K6 I > think, extrapolated
This is very interesting, I'd be eager to read that. Do you approximately remember what terms were in the name of the patent, to search for? AMD owns over eleven thousand patents... -----"gem5-users" <gem5-users-boun...@gem5.org> wrote: ----- To: "gem5 users mailing list" <gem5-users@gem5.org> From: "Gabe Black" Sent by: "gem5-users" Date: 03/22/2020 11:33PM Subject: Re: [gem5-users] Resources about the x86 microops in gem5 I would actually suggest the AMD manuals instead of the Intel ones, although neither will tell you how instructions are decoded into microops since that's a proprietary implementation detail which varies from CPU to CPU. The microcode ISA I used I got mostly from an AMD patent from the K6 I think, extrapolated and expanded on slightly (particularly for floating point stuff) since then. If you want to see specifically how the instructions are implemented in microcode, you can look at src/arch/x86/isa/insts, organized roughly as they are in the AMD manuals, or at least as they were 10 or so years ago. Gabe On Sun, Mar 22, 2020 at 9:13 AM Abhishek Singh <abhishek.singh199...@gmail.com> wrote: Hi, You can refer Intel manual it gives you complete explanation Also somewhere in the code I don’t remember exactly but there was a reference to particular intel manual Also refer to older mail threads which tell about x86 instruction deciding On Sun, Mar 22, 2020 at 12:02 PM Anis Peysieux <anis.peysi...@inria.fr> wrote: Hello, I wonder how the decomposition of macroops in microops were decided for x86 in gem5 (for example, DIV in div1, div2, div2i, br, divq and divr). Are there some resources that helped to know which microops are used in real-world CPU? Thanks, Anis. -- Anis Peysieux Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E301, Campus de Beaulieu, 35042 Rennes Cedex, France _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list gem5-users@gem5.org https://urldefense.proofpoint.com/v2/url?u=http-3A__m5sim.org_cgi-2Dbin_mailman_listinfo_gem5-2Dusers&d=DwIGaQ&c=sPZ6DeHLiehUHQWKIrsNwWp3t7snrE-az24ztT0w7Jc&r=ecC5uu6ubGhPt6qQ8xWcSQh1QUJ8B1-CG4B9kRM0nd4&m=4Q8Qzgx14F3sjNE2ThTh1SYBkCAO9zhw7s7p3qblQfQ&s=w_xUAZqtNXOMCCQgJo_A8u3y6IQMRRPAHn8JHP7K4IY&e= _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
