Private vs Shared L2 depends on the coherence protocol you use. The coherence protocol exposes the total number of controllers (L1/L2/Dir) which you can connect whatever way you want. Similarly, if you have a shared L2, I think the coherence protocol can expose multiple NUCA slices or a single one. [I am not familiar with the latest in terms of the coherence protocols in gem5 today].
There does not need to be a one L2 per core — the Mesh_* is an example topology file which assumes there are equal number of L1s and L2s and connects them to all routers. You can see MeshDirCorners_* where you can see how you can connect different number of L1s, L2s and Directories. Cheers, Tushar On Oct 13, 2020, 1:16 PM -0400, Farhad Yusufali via gem5-users <gem5-users@gem5.org>, wrote: Hi all, I'm trying to simulate a multicore system that uses a Mesh XY topology, and has a single shared L2. However, the documentation here (http://www.m5sim.org/Interconnection_Network) says the following: Mesh_*: This topology requires the number of directories to be equal to the number of cpus. The number of routers/switches is equal to the number of cpus in the system. Each router/switch is connected to one L1, one L2 (if present), and one Directory. The number of rows in the mesh has to be specified by --mesh-rows. This parameter enables the creation of non-symmetrical meshes too. Since there needs to be one L2 per core, I assume the L2s are private. (Unless I'm misunderstanding and these are just NUCA slices of one shared L2?). How can I go about using a Mesh_XY topology with a shared L2 cache? Thanks, Farhad
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