If private/shared is determined by the coherence protocol, what does the "number of L2 caches" represent? For instance, I'm using the MESI Two Level protocol, which according to http://www.m5sim.org/MESI_Two_Level uses a shared L2 cache. However, even when using this I can have multiple L2 caches using the "--num-l2caches" parameter. What does it mean to have multiple shared caches? I thought by definition a shared cache meant a singular cache.
Thanks, Farhad ________________________________ From: Krishna, Tushar via gem5-users <[email protected]> Sent: October 13, 2020 1:43 PM To: gem5 users mailing list <[email protected]> Cc: Krishna, Tushar <[email protected]> Subject: [gem5-users] Re: Shared L2 with Mesh XY Topology EXTERNAL EMAIL: Treat content with extra caution. Private vs Shared L2 depends on the coherence protocol you use. The coherence protocol exposes the total number of controllers (L1/L2/Dir) which you can connect whatever way you want. Similarly, if you have a shared L2, I think the coherence protocol can expose multiple NUCA slices or a single one. [I am not familiar with the latest in terms of the coherence protocols in gem5 today]. There does not need to be a one L2 per core — the Mesh_* is an example topology file which assumes there are equal number of L1s and L2s and connects them to all routers. You can see MeshDirCorners_* where you can see how you can connect different number of L1s, L2s and Directories. Cheers, Tushar On Oct 13, 2020, 1:16 PM -0400, Farhad Yusufali via gem5-users <[email protected]>, wrote: Hi all, I'm trying to simulate a multicore system that uses a Mesh XY topology, and has a single shared L2. However, the documentation here (http://www.m5sim.org/Interconnection_Network) says the following: Mesh_*: This topology requires the number of directories to be equal to the number of cpus. The number of routers/switches is equal to the number of cpus in the system. Each router/switch is connected to one L1, one L2 (if present), and one Directory. The number of rows in the mesh has to be specified by --mesh-rows. This parameter enables the creation of non-symmetrical meshes too. Since there needs to be one L2 per core, I assume the L2s are private. (Unless I'm misunderstanding and these are just NUCA slices of one shared L2?). How can I go about using a Mesh_XY topology with a shared L2 cache? Thanks, Farhad
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