On 10/22/2020 1:26 PM, Muhammad Aamir via gem5-users wrote:
Hi, the miss rates are exactly the same when using the in-order CPU for both when using level 1 cache alone and using it with level 1 and 2 cache. For O3CPU, there is a very minor difference (i.e. a difference of 0.01) but almost the same. This shouldn't be the case, if I only have one level of cache should I not have a higher miss rate in it compared to when using it together with a l2 cache? especially in the case of random accesses to the memory?
I think you're confusing miss rate with number of accesses that go to memory to be served. The miss rate is going to be the L1 miss rate, and as a previous poster pointed out, that's not going to change no matter what L2, L3, etc., arrangement you might have.
Further, I think adding together the number of L1 and L2 miss rates (say) is a somewhat non-sensical thing to do. I think maybe what you're reaching for would be "what fraction of accesses end up at main memory". I agree that inserting an L2 cache would cause that to go down. You can probably get the desired numbers by referring to other statistics.
So, I think this is just a confusion of terminology, not a problem in gem5. Best wishes -- EM _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
