[gem5-users] How to modify the gem5 simulator code?

[백승수 via gem5-users]

Hi.


I built a system that has two cpu that have private L1 caches, shared L2
caches, memory controller that has nvm and dram.



Workload has been assigned to each cpu.



I want to use only the dram for cpu0 and nvm for cpu1.



Therefore, I thought it was necessary to modify some of the code on the
simulator. However, it is difficult to find where the simulation of the
memory access request occurs.



Could you tell me where the code for processing memory access requests in
the simulator is?



Thank you for reading it.

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