Hi, The files you want to look at for the memory access are src/mem/ dram_ctrl.cc/.hh and src/mem/DRAMCtrl.py for issuing requests from the memory controller. The memory access itself is performed in DRAMCtrl::accessAndRespond, with a call to access() which is defined in src/mem/abstract_mem.cc.
This may have changed with recent gem5 updates but I don't think there is a field to identify the requesting core so you can differentiate between them, but perhaps adding a field in the packet class definition and assigning the threadID would help you do that. Sincerely, - Alex
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