Hi Jason,
We are planning to implement and test CXL protocol/model with gem5, and I've
seen your reply about CXL implementation
(https://www.mail-archive.com/gem5-users@gem5.org/msg18881.html). Before diving
into the code, I have some questions about implementation. Could you please
provide some tips? Thanks!​
1. Could it be implemented in SE mode? It seems to be complicated with the OS
layer and driver layer in FS mode, and we want to firstly implement an initial
model (e.g., a type 1 (cxl.io + cxl.cache) or type 3 (cxl.io + cxl.mem) device)
as simple as possible.
2. Could the cxl.cache/mem sub-protocol ​be implemented in SLICC? How to treat
and implement the cxl.io sub-protocol (which is PCIe-like)?
3. What kind of SimObject should be implemented roughly (CXLDevice,
CXLController, etc.)?​ Should the CXLDevice be inherited from PciDevice class?
Thank you very much!
Best Regards,
Zicong Wang
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