Hi Zicong, 1. I personally don't believe that CXL in SE mode would be very interesting. From my point of view, CXL would be interesting only to capture the OS and system-level effects. That said, you may be able to test CXL.cache in SE mode.
2. To implement the different protocols: CXL.io: This would be extending the PCI devices in gem5/src/dev. This part of the protocol will need to be implemented functionally to get the OS drivers to work correctly. CXL.mem: This should be quite straightforward to implement without any changes to any coherence protocols. This part of CXL would just be setting up the memory ranges correctly and hooking it into CXL.io. I would start with this one. CXL.cache: To model the coherence in CXL.cache, you will need to add and/or modify a new Ruby coherence protocol. To get this to work, you'll first have to have CXL.io and be able to figure out how to communicate the memory ranges (like CXL.mem). 3. CXLDevice would most likely inherit from PciDevice. The other devices would be whatever you want them to be (e.g., a GPU which speaks CXL.cache or a memory device that speaks CXL.mem). Then these devices would "register" with the CXLDevice and through the configuration file you will hook up the other devices in the protocol. The most complex part of all of this will be the configuration. I would suggest trying to make the configuration as modular as possible. The examples in the standard library should help. I've given this some thought, but I haven't started implementing anything. I'm sure that the process I outlined above will change as you start diving into things. Cheers, Jason On Fri, Mar 25, 2022 at 1:35 AM Zicong Wang via gem5-users < gem5-users@gem5.org> wrote: > Hi Jason, > > We are planning to implement and test CXL protocol/model with gem5, and > I've seen your reply about CXL implementation ( > https://www.mail-archive.com/gem5-users@gem5.org/msg18881.html). Before > diving into the code, I have some questions about implementation. Could you > please provide some tips? Thanks!​ > > 1. Could it be implemented in SE mode? It seems to be complicated with > the OS layer and driver layer in FS mode, and we want to firstly implement > an initial model (e.g., a type 1 (cxl.io + cxl.cache) or type 3 (cxl.io + > cxl.mem) device) as simple as possible. > > 2. Could the cxl.cache/mem sub-protocol ​be implemented in SLICC? How to > treat and implement the cxl.io sub-protocol (which is PCIe-like)? > > 3. What kind of SimObject should be implemented roughly (CXLDevice, > CXLController, etc.)?​ Should the CXLDevice be inherited from PciDevice > class? > > Thank you very much! > > > Best Regards, > > Zicong Wang > > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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