Hi EM,
Thanks again
Let me make a summary, I organize my steps of multi-core restore
checkpoint as follows:
Step 1: Generate BBV files on a single-core system using gem5/qemu
Step 2: Generate checkpoints on multi-core systems using gem5/qemu
Step 3: In order to make multi-core visible on the linux/android
kernel, the dtb file needs to be modified. Perform the following operations on
the kernel code:
$ cp ./arch/arm/boot/dts/vexpress-v2p-ca15-tc1-gem5.dts
./arch/arm/boot/dts/vexpress-v2p-ca15-tc1-gem5_4cpus.dts
$ vim ./arch/arm/boot/dts/vexpress-v2p-ca15-tc1-gem5_4cpus.dts
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
clock-frequency = <1000000000>;
};
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <3>;
+ };
};
$dtc -I dts -O dtb
./arch/arm/boot/dts/vexpress-v2p-ca15-tc1-gem5_4cpus.dts >
vexpress-v2p-ca15-tc1-gem5_4cpus.dtb
Step 4: Run gem5 to simulate a multi-core system using the new
dtb file. : --dtb-filename=vexpress-v2p-ca15-tc1-gem5_4cpus.dtb
$build/ARM/gem5.opt configs/example/fs.py \
--caches --l2cache --l1i_size=32kB \
--l1d_size=32kB --l2_size=1MB --l2_assoc=2 \
--sys-clock=1600MHz \
--cpu-type=DerivO3CPU\
--mem-type=SimpleMemory \
--os-type=android-kitkat
--disk-image=myimage.img --machine-type=VExpress_EMM
--dtb-filename=vexpress-v2p-ca15-tc1-gem5_4cpus.dtb --kernel=vmlinux \
-n 4 --mem-size=1800MB --frame-capture \
--restore-simpoint-checkpoint -r 1
--checkpoint-dir /data01/linansong/my_tools/gem5/gem5/m5out/testO3CPU.h264.CPT/
Then all the CPI in stats.txt look normal
system.switch_cpus0.cpi 1.003656 #
CPI: Cycles Per Instruction
system.switch_cpus0.cpi_total 1.003656 #
CPI: Total CPI of All Threads
system.switch_cpus1.cpi 0.577311 #
CPI: Cycles Per Instruction
system.switch_cpus1.cpi_total 0.577311 #
CPI: Total CPI of All Threads
system.switch_cpus2.cpi 0.859439 #
CPI: Cycles Per Instruction
system.switch_cpus2.cpi_total 0.859439 #
CPI: Total CPI of All Threads
system.switch_cpus3.cpi 1.010280 #
CPI: Cycles Per Instruction
system.switch_cpus3.cpi_total 1.010280 #
CPI: Total CPI of All Threads
system.switch_cpus0.cpi 0.805151 #
CPI: Cycles Per Instruction
system.switch_cpus0.cpi_total 0.805151 #
CPI: Total CPI of All Threads
system.switch_cpus1.cpi 0.791778 #
CPI: Cycles Per Instruction
system.switch_cpus1.cpi_total 0.791778 #
CPI: Total CPI of All Threads
system.switch_cpus2.cpi 1.391547 #
CPI: Cycles Per Instruction
system.switch_cpus2.cpi_total 1.391547 #
CPI: Total CPI of All Threads
system.switch_cpus3.cpi 0.898717 #
CPI: Cycles Per Instruction
system.switch_cpus3.cpi_total 0.898717 #
CPI: Total CPI of All Threads
Thanks
-----邮件原件-----
发件人: Eliot Moss <m...@cs.umass.edu>
发送时间: 2022年12月28日 21:12
收件人: The gem5 Users mailing list <gem5-users@gem5.org>
抄送: 张文军-软件 <zhangwenjunr...@vivo.com>; 钟婷 <zhongt...@vivo.com>; 夏亚东
<yadong....@vivo.com>; 李南松 <linans...@vivo.com>
主题: Re: [gem5-users] 答复: 答复: 答复: Re: [Multi-core restore checkpoint failed]
On 12/28/2022 4:09 AM, 李南松 via gem5-users wrote:
> Hi EM,
>
> I have found the root cause of this issue.
> My multicore system didn't really work because I didn't modify the dtb
> file.
> So only one cpu is visible in my system /proc/cpuinfo file.
> After recompiling the multi-core dtb file, the data of other cores in
> stats.txt is also normal
Ok - sorry if my response was not on target! EM
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