Hi, all
I am using M5 2.0.5 in SE mode to do cache bahavior simulation.
First, I excute gzip for 0.7 billion in a single core, and its L2 cache
miss rate is 46.2%, cpi is 2.166.
Then I construct a two core system with private L1 cache and shared L2
cache. L1 and L2 cache's parameters are not changed compared with single
core. I execute gzip and art in this two core system, and each benchmark
is bound to a core. The parameter max_insts_any_thread is set to 0.7 billion.
Then, the gzip's miss rate in L2 cache is changed to 59.5% with only 13.3%
decrease, and cpi is changed to 2.615.
But in many papers, gzip's L2 cache miss number is increased 9X when it
is excuted with art, and ipc could also change 60%.
Is it the reason that executed instruction number is too small, or the
problem of M5 configuration?
My L1 icache and dcache is 2-way associative and 8kB, and shared L2 cache is
16-way associative and 512kB. The detailed configuration is listed in accessory.
By the way, the L2 cache miss rate distinction of gzip when L2 size
changed in 2.0.4 is very tinny. L2 cache miss rate for gzip is 63% with
1MB L2, and is 64.5% with 512kB L2. But the distinction is more obvious
in 2.0.5.
So I think may be the simulation of cache part in M5 has some problem.
Could anyone tell me why? or any possible reasons?
Thanks a lot!
Jason
import m5
from m5.objects import *
m5.AddToPath('../configs/common')
# --------------------
# Base L1 Cache
# ====================
class L1(BaseCache):
assoc = 2
block_size = 64
latency = '1ns'
mshrs = 5
tgts_per_mshr = 8
write_buffers = 4
# ----------------------
# Base L2 Cache
# ----------------------
class L2(BaseCache):
assoc = 16
block_size = 64
latency = '6ns'
mshrs = 16
tgts_per_mshr = 24
write_buffers = 24
#repl = 'Lru'
nb_cores = 2
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus,
physmem=PhysicalMemory(range=AddrRange("512MB"),latency='80ns'),
membus = Bus(clock='1000MHz'))
# connect memory to membus
system.physmem.port = system.membus.port
# add private L1 and L2 caches
system.toL2Bus = Bus()
system.l2c = L2(size = '512kB')
system.l2c.cpu_side = system.toL2Bus.port
#system.l2c.mem_side = system.membus.port
for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '8kB'),
L1(size = '8kB'))
#system.l2c.mem_side = system.membus.port
# the shared configuration of the cpus are set here
cpu.clock = '4GHz'
cpu.max_insts_any_thread= '700000000'
cpu.numROBEntries=256
cpu.LQEntries=64
cpu.SQEntries=64
cpu.numThreads=1
cpu.connectMemPorts(system.toL2Bus)
system.l2c.mem_side = system.membus.port
# -----------------------
# run simulation
# -----------------------
root = Root( system = system )
root.system.mem_mode = 'timing'
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