Actually, I want the busports of shared bus to provide tport-like functionality. So, everytime there is a transaction from l2 cache(private) to l3 cache (shared), if i attempt to store the packet (say in a queue or just a packetptr associated with each busport) to send it through a set of buses by scheduling events (currently if u connect several buses together, recvTiming is called immediately on all of them) without toucing any of its fields, i have mshrdownstreampending problems. Its sortof confusing, while the packet is passing through the bus, caches from above keep checking markPending, inservice and downstreampending fields (mycache()->markInService etc).
---- Original message ---- >Date: Fri, 10 Oct 2008 17:39:59 -0700 >From: "Steve Reinhardt" <[EMAIL PROTECTED]> >Subject: Re: [m5-users] MSHR downStreamPending >To: "M5 users mailing list" <[email protected]> > > Off the top of my head I can't really say. I don't > see any obvious reason why this wouldn't work. I'd > trace through a miss with gdb and see if/when the > packet pointer field gets modified during the > transaction. > > Steve > > On Thu, Oct 9, 2008 at 10:38 PM, Shoaib Akram > <[EMAIL PROTECTED]> wrote: > > Thanks for the reply. I created a module that > interfaces two buses, simply receives packets from > a bus (connected above to l2 cache) , extract the > senderState field, set the downstreampending, > inservice and markPending fields acordingly and > sends it to shared l3 cache below. However, when > response reaches the l2 cache, i get segmentation > fault at this point. > std::memcpy(blk->data, pkt->getPtr<uint8_t>(), > Is it because I corrupted the packet as it was > sent from the cache above(l2) to cache below(l3). > ---- Original message ---- > >Date: Mon, 6 Oct 2008 07:00:22 -0700 > >From: "Steve Reinhardt" <[EMAIL PROTECTED]> > >Subject: Re: [m5-users] MSHR downStreamPending > >To: "M5 users mailing list" <[email protected]> > > > > Ali's right... the bridge wasn't designed to > support > > coherence (just I/O accesses), or conversely > > coherence wasn't designed to support bridges. > > > > You could build a module that does what you > want and > > supports coherence; basically it would have to > act > > like a 0-byte cache. It would need to forward > > express snoops as Ali mentioned, and also do > some > > request/response matching, and probably keep > MSHRs > > too. > > > > Of course, the M5 coherence protocol was not > > developed to be ultra-realistic (see > > > http://m5sim.org/wiki/index.php/Coherence_Protocol), > > so if you're proposing a new style of > interconnect > > then you probably really want to implement a > more > > realistic protocol to give yourself a more > realistic > > evaluation. It's not that hard to do so if > you have > > a fixed topology; most of the complexity and > > artificiality of the current model is because > it > > supports nearly arbitrary levels of cache and > > numbers of caches at each level. > > > > Steve > > > > On Sun, Oct 5, 2008 at 9:39 PM, Shoaib Akram > > <[EMAIL PROTECTED]> wrote: > > > > In case Steve wants a closer look at the > system > > being implemented, attached is a pdf file. > The > > shared bus I am implementing is a bit > complex than > > I explained below. > > ---- Original message ---- > > >Date: Mon, 6 Oct 2008 00:03:54 -0400 > > >From: Ali Saidi <[EMAIL PROTECTED]> > > >Subject: Re: [m5-users] MSHR > downStreamPending > > >To: M5 users mailing list > <[email protected]> > > > > > >The bridge isn't supported in the middle of > a > > coherent hierarchy. > > >Steve can probably comment more about why, > but > > minimally it would need > > >to support passing the express-snoops and > it > > currently doesn't. > > > > > >Ali > > > > > >On Oct 5, 2008, at 11:21 PM, Shoaib Akram > wrote: > > > > > >> I am simulating a multiprocessor system > with a > > shared bus. Private > > >> L1,l2 and shared L3 (connected to shared > bus > > through tol3bus). When > > >> I insert a bridge between the shared bus > and > > tol3bus, the L2 cache > > >> on a miss, after allocating mshr and > sending > > the bus packet on > > >> shared bus, calls > cleardownStreamPending(). > > This is not supposed to > > >> happen since cleardownStreamPending() > should be > > called by last- > > >> level(L3) cache. cleardownStreamPending() > is > > indeed called by the L3 > > >> cache if there is no bridge. Any of the > > developers aware of the > > >> implementation of this feature can throw > some > > light maybe? > > >> > _______________________________________________ > > >> m5-users mailing list > > >> [email protected] > > >> > > > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > >> > > > > > > >_______________________________________________ > > >m5-users mailing list > > >[email protected] > > > >http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > _______________________________________________ > > m5-users mailing list > > [email protected] > > > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > >________________ > >_______________________________________________ > >m5-users mailing list > >[email protected] > >http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >________________ >_______________________________________________ >m5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/m5-users _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
