Ah, um. I do not use checkpointing in M5 and have never tested doing
it with DRAMsim. I'm not sure that DRAMsim itself has any
functionality to perform checkpointing, which would be necessary to
enable such operation.
On Feb 18, 2009, at 5:44 PM, Angela Carlsson wrote:
Hello Clint,
I get an error checkpointing when I am using DRAMSim, this is the
error
m5.debug: build/ALPHA_FS/python/swig/pyevent.cc:84: void
cleanupCountedDrain(Event*): Assertion `event->getCount() == 0'
failed.
Program received signal SIGABRT, Aborted.
[Switching to Thread 47618140672304 (LWP 11420)]
0x0000003175f2f765 in raise () from /lib64/libc.so.6
I just want to ask you if you experience the same problem when you
are trying to checkpoint in FS. If you found this problem and you
solved it can you please post the answer?.
Thanks a lot in advance.
> Date: Fri, 23 Jan 2009 12:41:10 -0500
> From: [email protected]
> To: [email protected]
> Subject: [m5-users] [PATCH] Beta patch for M5 2.0 DRAMsim
implemention
>
> # HG changeset patch
> # User Clint Smullen <[email protected]>
> # Date 1232732406 18000
> # Node ID a95dd3a28ecb82a074de030367fe641d52aaf148
> # Parent 0397aa216e2290a50fb7138bd28563926573c929
> Beta patch for M5 2.0 DRAMsim implemention.
>
> NOTE: None of the DRAMsim files meet the M5 style requirements, so
if that
> module is enabled, it will present a large series of messages when
you try
> to apply the patch.
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