Are you concerned that the total number of accesses is small, or just that there are few concurrent accesses? If it's the former, I'm stumped too, and I wold suggest turning on some tracing (e.g., start with --trace-flags=Cache) and you can see what's going on during the simulation.
If it's the latter, I think the reason is that you're using TimingSimpleCPU which models a blocking pipeline, so you're not going to have more than one outstanding access from each CPU at any point in time. Thus it's not surprising that you rarely see more than two total. If you want non-blocking behavior from the CPUs you'll need to use the O3 CPU model. Steve On Thu, Feb 19, 2009 at 11:09 PM, Bob Nagel <[email protected]> wrote: > Hello all, > > I am testing PARSEC benchmarks in FS along with DRAMSim and I get very > few accesses to the memory. Normally I do not have more than 2 > petitions waiting to be processed. If I increase the latency of the > memory I still get very few accesses, and the size of the caches I am > using is really small. I consider that this is a problem of my > configuration of the simulator. In my rcS I am trying to execute 4 > benchmarks at the same time using the & operator, I have something > like this: > > ...250k.dat 220 & > ...rret/output.txt & > ...mate/out.fluid & > ...eal/1000.nets > /sbin/m5 exit > The execution of the benchmarks is right all of them finish > successfully. But I do not know if all of them are running at the same > time. > > I do not know if using & will work in M5, if this is not the right way > to execute the 4 benchs at the same time. Can anyone please provide a > way to do this in FS?. > > > Also regarding the few accesses and my configuration, this are some of > the main parameters I have in the FS.py: > L2Cache(size = '8kB', assoc = 4, latency = '7.5ns', block_size = 64, > mshrs = 64 ) > SplitL1Caches(L1Cache(size = '4kB', assoc = 2, latency = '0.5ns', > block_size = 64, mshrs = 64 ), > L1Cache(size = '4kB', assoc = 2, latency = > '0.5ns', block_size = 64, mshrs = 64 )) > > As you can see those cache are really small. And I think I should get > much more petitions waiting to be processed in DRAMsim. I have tried > different benchmarks but in none of them I get a big amount of > accesses. Does anyone know what am I missing in the configuration?. > > Thanks a lot in advance. > > > And finally if someone need this is my config.ini file: >
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