I have attached a diagram(pdf file) of configuration and fs2.py. Please note that the problem occurs because of l3Bridge (commented in fs2.py).
Ofcourse, I have a solution to maintain coherence at the back end. ---- Original message ---- >Date: Mon, 4 May 2009 15:04:57 -0400 >From: "Geoffrey Blake" <[email protected]> >Subject: Re: [m5-users] Range Error >To: "'M5 users mailing list'" <[email protected]> > >If you haven't modified any code, it is most likely with how your fs.py >configures the devices. You have to make sure no device can pass its >address range back through multiple paths (ie. devices cannot be connected >to multiple bridges that connect to one bus), and no two devices have the >same address ranges set. The best way is to post your fs.py file so some >here can help if they are able. > >Geoff > >-----Original Message----- >From: [email protected] [mailto:[email protected]] On >Behalf Of Shoaib Akram >Sent: Monday, May 04, 2009 2:40 PM >To: [email protected] >Subject: [m5-users] Range Error > >I am getting a "Two devices with same range" error. I have never been >involved with the Range business. Can some one give hints as to where to >look for the problem. I am running fs.py with a few extra bridges. Is this >problem need to be resolved at the front-end or tweaking bus.cc? >_______________________________________________ >m5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > >No virus found in this incoming message. >Checked by AVG - www.avg.com >Version: 8.5.287 / Virus Database: 270.12.16/2094 - Release Date: 05/03/09 >16:51:00 > >_______________________________________________ >m5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
cluster.pdf
Description: Adobe PDF document
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Authors: Ali Saidi
import optparse, os, sys
import m5
if not m5.build_env['FULL_SYSTEM']:
m5.panic("This script requires full-system mode (*_FS).")
from m5.objects import *
m5.AddToPath('../common')
from FSConfig import *
from SysPaths import *
from Benchmarks import *
import Simulation
from Caches import *
# Get paths we might need. It's expected this file is in m5/configs/example.
config_path = os.path.dirname(os.path.abspath(__file__))
config_root = os.path.dirname(config_path)
parser = optparse.OptionParser()
# System options
parser.add_option("--kernel", action="store", type="string")
parser.add_option("--script", action="store", type="string")
parser.add_option("-D","--delay", action="store", type=int)
# Benchmark options
parser.add_option("--dual", action="store_true",
help="Simulate two systems attached with an ethernet link")
parser.add_option("-b", "--benchmark", action="store", type="string",
dest="benchmark",
help="Specify the benchmark to run. Available benchmarks: %s"\
% DefinedBenchmarks)
# Metafile options
parser.add_option("--etherdump", action="store", type="string", dest="etherdump",
help="Specify the filename to dump a pcap capture of the" \
"ethernet traffic")
execfile(os.path.join(config_root, "common", "Options.py"))
(options, args) = parser.parse_args()
if args:
print "Error: script doesn't take any positional arguments"
sys.exit(1)
# driver system CPU is always simple... note this is an assignment of
# a class, not an instance.
DriveCPUClass = AtomicSimpleCPU
drive_mem_mode = 'atomic'
# system under test can be any CPU
(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
TestCPUClass.clock = '2GHz'
DriveCPUClass.clock = '2GHz'
if options.benchmark:
try:
bm = Benchmarks[options.benchmark]
except KeyError:
print "Error benchmark %s has not been defined." % options.benchmark
print "Valid benchmarks are: %s" % DefinedBenchmarks
sys.exit(1)
else:
if options.dual:
bm = [SysConfig(), SysConfig()]
else:
bm = [SysConfig()]
if m5.build_env['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
elif m5.build_env['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
elif m5.build_env['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0])
elif m5.build_env['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, bm[0])
else:
m5.panic("incapable of building non-alpha or non-sparc full system!")
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
np = options.num_cpus
delay=options.delay
test_sys.membus.header_cycles=delay
test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
if options.caches:
test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
test_sys.iocache.cpu_side = test_sys.iobus.port
test_sys.iocache.mem_side = test_sys.membus.port
test_sys.l3=L3Cache(size='1MB')
#test_sys.l3bridge=Bridge()
test_sys.tol3bus1=Bus()
test_sys.tol3bus2=Bus()
test_sys.tol3bus=Bus()
test_sys.l3.cpu_side=test_sys.tol3bus.port
test_sys.l3.mem_side=test_sys.membus.port
test_sys.tol3bus1.port=test_sys.tol3bus.port
test_sys.tol3bus2.port=test_sys.tol3bus.port
#test_sys.tol3bus1.port=test_sys.l3bridge.side_a
#test_sys.l3bridge.side_b=test_sys.tol3bus2.port
for i in xrange(np-2):
if options.caches:
test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
test_sys.cpu[i].l2 = L2Cache(size = '128kB')
test_sys.cpu[i].tol2bus = Bus()
test_sys.cpu[i].l2.cpu_side = test_sys.cpu[i].tol2bus.port
test_sys.cpu[i].l2.mem_side = test_sys.tol3bus1.port
test_sys.cpu[i].connectMemPorts(test_sys.cpu[i].tol2bus)
for i in xrange(np-2,np):
if options.caches:
test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
test_sys.cpu[i].l2 = L2Cache(size = '128kB')
test_sys.cpu[i].tol2bus = Bus()
test_sys.cpu[i].l2.cpu_side = test_sys.cpu[i].tol2bus.port
test_sys.cpu[i].l2.mem_side = test_sys.tol3bus2.port
test_sys.cpu[i].connectMemPorts(test_sys.cpu[i].tol2bus)
if m5.build_env['TARGET_ISA'] == 'mips':
setMipsOptions(TestCPUClass)
if len(bm) == 2:
if m5.build_env['TARGET_ISA'] == 'alpha':
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
elif m5.build_env['TARGET_ISA'] == 'mips':
drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
elif m5.build_env['TARGET_ISA'] == 'sparc':
drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
elif m5.build.env['TARGET_ISA'] == 'x86':
drive_sys = makeX86System(drive_mem_mode, bm[1])
drive_sys.cpu = DriveCPUClass(cpu_id=0)
drive_sys.cpu.connectMemPorts(drive_sys.membus)
if options.fastmem:
drive_sys.cpu.physmem_port = drive_sys.physmem.port
if options.kernel is not None:
drive_sys.kernel = binary(options.kernel)
root = makeDualRoot(test_sys, drive_sys, options.etherdump)
elif len(bm) == 1:
root = Root(system=test_sys)
else:
print "Error I don't know how to create more than 2 systems."
sys.exit(1)
Simulation.run(options, root, test_sys, FutureClass)
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