I remember that Korey had pointed out that the sim_insts reported for O3 does not count nop instructions. What the number of instructions that the commit stage commits? Is that number very close to 10 billion and 1?
regards, Soumyaroop On Sat, Apr 10, 2010 at 10:05 PM, Sage <[email protected]> wrote: > Hi, everyone, > > I have a question concerning the implication of statistics in the > m5out/stats.txt . The following is the statistics of a benchmark that I > checkpointed at 10,000,000,000,000 ticks. "sim_insts" was expected to be > 10,000,000,000 in my mind, which however turns out to be another value > finally. But the sum of ITB.fetch_hits and ITB.fetch.misses is still > 10,000,000,001. My question is why "sim_insts" is very different from > "itb.fetch_hits + itb.fetch_misses". Does anyone know the underlying > reasons? > > Thanks, > Leonard > > > > ---------- Begin Simulation Statistics ---------- > host_inst_rate 2271214 > # Simulator instruction rate (inst/s) > host_mem_usage 2182452 > # Number of bytes of host memory used > host_seconds 4399.15 > # Real time elapsed on the host > host_tick_rate 2273167381 > # Simulator tick rate (ticks/s) > sim_freq 1000000000000 > # Frequency of simulated ticks > *sim_insts 9991406168 > # Number of instructions simulated* > sim_seconds 10 > # Number of seconds simulated > sim_ticks 10000000000000 > # Number of ticks simulated > system.cpu.dtb.data_accesses 2723153832 > # DTB accesses > system.cpu.dtb.data_acv 0 > # DTB access violations > system.cpu.dtb.data_hits 2714560029 > # DTB hits > system.cpu.dtb.data_misses 8593803 > # DTB misses > system.cpu.dtb.fetch_accesses 0 > # ITB accesses > system.cpu.dtb.fetch_acv 0 > # ITB acv > system.cpu.dtb.fetch_hits 0 > # ITB hits > system.cpu.dtb.fetch_misses 0 > # ITB misses > system.cpu.dtb.read_accesses 1648737880 > # DTB read accesses > system.cpu.dtb.read_acv 0 > # DTB read access violations > system.cpu.dtb.read_hits 1645683821 > # DTB read hits > system.cpu.dtb.read_misses 3054059 > # DTB read misses > system.cpu.dtb.write_accesses 1074415952 > # DTB write accesses > system.cpu.dtb.write_acv 0 > # DTB write access violations > system.cpu.dtb.write_hits 1068876208 > # DTB write hits > system.cpu.dtb.write_misses 5539744 > # DTB write misses > system.cpu.idle_fraction 0 > # Percentage of idle cycles > system.cpu.itb.data_accesses 0 > # DTB accesses > system.cpu.itb.data_acv 0 > # DTB access violations > system.cpu.itb.data_hits 0 > # DTB hits > system.cpu.itb.data_misses 0 > # DTB misses > system.cpu.itb.fetch_accesses 10000000001 > # ITB accesses > system.cpu.itb.fetch_acv 0 > # ITB acv > *system.cpu.itb.fetch_hits 9999999971 > # ITB hits* > *system.cpu.itb.fetch_misses 30 > # ITB misses* > system.cpu.itb.read_accesses 0 > # DTB read accesses > system.cpu.itb.read_acv 0 > # DTB read access violations > system.cpu.itb.read_hits 0 > # DTB read hits > system.cpu.itb.read_misses 0 > # DTB read misses > system.cpu.itb.write_accesses 0 > # DTB write accesses > system.cpu.itb.write_acv 0 > # DTB write access violations > system.cpu.itb.write_hits 0 > # DTB write hits > system.cpu.itb.write_misses 0 > # DTB write misses > system.cpu.not_idle_fraction 1 > # Percentage of non-idle cycles > *system.cpu.numCycles 10000000001 > # number of cpu cycles simulated* > system.cpu.num_insts 9991406168 > # Number of instructions executed > system.cpu.num_refs 2723153832 > # Number of memory references > system.cpu.workload.PROG:num_syscalls 31 > # Number of system calls > > ---------- End Simulation Statistics ---------- > > -- > Give our ability to our work, but our genius to our life! > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > -- Soumyaroop Roy Ph.D. Candidate Department of Computer Science and Engineering University of South Florida, Tampa http://www.csee.usf.edu/~sroy
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