On Mon, Apr 12, 2010 at 5:36 AM, Korey Sewell <[email protected]> wrote: >> My question is why "sim_insts" is very different from >> "itb.fetch_hits + itb.fetch_misses". Does anyone know the underlying >> reasons? > if I'm not mistaken, the SimpleCPU also models a very light form of > stalling. Whether that be from TLB misses, branches, etc. you just > need to double check the "tick()" code to be sure.
THere are stalls in TimingSimpleCPU but not in AtomicSimpleCPU. Note that sim_insts + dtb.data_misses + itb.fetch_misses == cpu.numCycles. Steve _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
