Hi, We found out that in the cache_impl.hh, if there is a miss, it calls sendatomic through memsideport - testsys.cpu.icache-mem_side_port, which in turn calls recvatomic through the peer port - testsys.tol2bus-p1 which is the bus. We are not able to understand the flow of the packet after this, how does the bus connect and send the packet to the L2?
-- Pritha Ghoshal
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