turn on the trace flags it might help try m5.opt --trace-help fs.py then to --trace-flags=cache,bus,mem maybe some others that should help
On Wed, Apr 21, 2010 at 1:42 AM, Pritha Ghoshal <[email protected]> wrote: > Hi, > > We found out that in the cache_impl.hh, if there is a miss, it calls > sendatomic through memsideport - testsys.cpu.icache-mem_side_port, which in > turn calls recvatomic through the peer port - testsys.tol2bus-p1 which is > the bus. We are not able to understand the flow of the packet after this, > how does the bus connect and send the packet to the L2? > > -- > Pritha Ghoshal > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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