Hello,
I'm having some problems running with 4 cores and a Nehalem-like cache in
the latest few updates of m5. Previously the three-level cache structure had
worked fine. Specifically, the error I am getting is:
build/ALPHA_FS/mem/cache/cache_impl.hh:909: void
Cache<TagStore>::handleResponse(Packet*) [with TagStore = LRU]: Assertion
`target->pkt->cmd == MemCmd::StoreCondReq || target->pkt->cmd ==
MemCmd::StoreCondFailReq' failed.
I have added this to Options.py:
parser.add_option("--l3cache", action="store_true")
I have also updated Caches.py and CacheConfig.py and they are attached. I
updated the kernel to a newer rev according to the directions on the web
page.
(gdb) print *target
$2 = {recvTime = 2238099124338, readyTime = 2238099127776, order = 643, pkt
= 0x5a66ea0, source = 0, markedPending = true}
(gdb) print *target->pkt
$4 = {<FastAlloc> = {_vptr.FastAlloc = 0xc4ce10, static Max_Alloc_Size =
512, static Log2_Alloc_Quantum = 3, static Alloc_Quantum = 8, static
Num_Buckets = 65,
static Num_Structs_Per_New =<optimized out>, static freeLists = {0x0,
0x0, 0x0, 0x0, 0x0, 0x59e3108, 0x0, 0x5a5ce28, 0x0, 0x59df018, 0x5a0cad0,
0x233ec90, 0x5a08e80,
0x0<repeats 22 times>, 0x5a01b00, 0x0<repeats 29 times>}},
<Printable> = {_vptr.Printable = 0xc4ce38}, static PUBLIC_FLAGS =<optimized
out>,
static PRIVATE_FLAGS =<optimized out>, static COPY_FLAGS = 15, static
SHARED = 1, static EXPRESS_SNOOP = 2, static SUPPLY_EXCLUSIVE = 4, static
MEM_INHIBIT = 8, static VALID_ADDR = 256,
static VALID_SIZE = 512, static VALID_SRC = 1024, static VALID_DST = 2048,
static STATIC_DATA = 4096, static DYNAMIC_DATA = 8192, static ARRAY_DATA =
16384, flags = {_flags = 28416},
cmd = {static commandInfo = 0x11d1480, cmd = MemCmd::SCUpgradeFailReq}, req
= 0x59dc650, data = 0x5a70d10 "\320N\250\005", addr = 17759616, size = 64,
src = 1, dest = -1, origCmd = {
static commandInfo = 0x11d1480, cmd = MemCmd::InvalidCmd}, time =
2238099124338, finishTime = 2238099126000, firstWordTime = 2238099127000,
static Broadcast = -1,
senderState = 0x25876b8}
It works fine with only the L2 cache, the problem is adding the L3 cache.
Any ideas?
Joe
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