Hi All,
I am trying to collect memory traces of the PARSEC benchmarks using M5 sim
in the timing cpu model of ALPHA_FS mode. Basically, I am interested in
collecting the PC of the Data memory access instructions, the virtual
addresses of the data references and corresponding physical addresses.
Upon exploring, I found the following
a) The PageTable class is defined for only the SE mode and is hence, not
relevant in my case
b) All the possible data virtual address->physical address translations for
ALPHA_FS is being done in the functions defined in src/arch/alpha/tlb.cc
file. But It seems that even if a virtual address doesn't hit in the TLB,
the corresponding page table walk is also done in the lookup function and
the TLB updated simultaneously? Is it correct?
So, based on the above observation, I am trying to tap the PC, virtual
address and physical addresses of individual memory access instructions in
the DataTranslation::finish function (defined in cpu/translation.hh) as
follows:
if(fault == NoFault && (!req->isPrefetch()))
req->getPC(), req->getPaddr(),req->getVaddr()
I just wanted to confirm if I am tapping the items at the right place? Or am
I missing something here?
Any help will be highly appreciated.
Thanks,
Reena
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