There is no support for the inorder CPU and the ARM ISA. Korey has been looking at providing some, but I don't know that he has gotten very far yet. The out-of-order CPU works in SE mode as do the simple cpus.
Ali On Mon, 31 Jan 2011 12:51:21 -0500, Andrew Lukefahr wrote: Hi, If I try to run $ ./build/ARM_SE/m5.debug configs/example/se.py --inorder --caches I get this.... ... command line: ./build/ARM_SE/m5.debug configs/example/se.py --inorder --caches Traceback (most recent call last): File "", line 1, in File "/home/andyrewbobb/m5/src/python/m5/main.py", line 359, in main exec filecode in scope File "configs/example/se.py", line 138, in (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) File "/home/andyrewbobb/m5/configs/common/Simulation.py", line 54, in setCPUClass class TmpClass(InOrderCPU): pass NameError: global name 'InOrderCPU' is not defined Am I missing another option? Thanks Andrew Lukefahr [email protected] [1] Open Source, Open Minds Links: ------ [1] mailto:[email protected]
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