As Ali states, Progress on arm-inorder has been slow so far as development to actual speed up the model has taken some precedence over the ARM port.
However, I would say check back toward the end of the month (if you are still interested in this aspect of M5 at that point.) On Mon, Jan 31, 2011 at 12:58 PM, Ali Saidi <[email protected]> wrote: > There is no support for the inorder CPU and the ARM ISA. Korey has been > looking at providing some, but I don't know that he has gotten very far yet. > The out-of-order CPU works in SE mode as do the simple cpus. > > > > Ali > > > > > > On Mon, 31 Jan 2011 12:51:21 -0500, Andrew Lukefahr < > [email protected]> wrote: > > Hi, > > If I try to run > $ ./build/ARM_SE/m5.debug configs/example/se.py --inorder --caches > > I get this.... > > ... > command line: ./build/ARM_SE/m5.debug configs/example/se.py --inorder > --caches > Traceback (most recent call last): > File "", line 1, in > File "/home/andyrewbobb/m5/src/python/m5/main.py", line 359, in main > exec filecode in scope > File "configs/example/se.py", line 138, in > (CPUClass, test_mem_mode, FutureClass) = > Simulation.setCPUClass(options) > File "/home/andyrewbobb/m5/configs/common/Simulation.py", line 54, in > setCPUClass > class TmpClass(InOrderCPU): pass > NameError: global name 'InOrderCPU' is not defined > > > Am I missing another option? > > Thanks > > > Andrew Lukefahr > [email protected] > > Open Source, Open Minds > > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > -- - Korey
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