Hi, First, I'm not too concerned w/InOrder at the moment, I just didn't realize that TimingSimple and InOrder were different.
Second, I've got a SimObject (which I'm calling TraceCache for lack of a better term). I'm trying to create a hook in the TimingSimple CPU to call my TraceCache object. My question is how do I reference it? I'm assuming I need a reference for it in the .py script and in the .hh file. But I'm not sure how to "connect" my TraceCache to a TimingSimpleCPU. Do I need to specify it as an additional parameter when I create the CPU? If I do that, do I need to modify the "tree" (eg TimingSimpleCPU, BaseSimpleCPU, BaseCPU, etc) to support the additional parameter? Thanks Andrew Lukefahr [email protected] Open Source, Open Minds On Fri, Jan 28, 2011 at 4:42 PM, Gabriel Michael Black < [email protected]> wrote: > Quoting Andrew Lukefahr <[email protected]>: > > Hi, >> >> I managed to create my own SimObject, and get that to compile/run into m5. >> Now I want my SimObject track each pc on commit. How can I get m5 to call >> a >> function in my object when the pc changes? Is there some event based >> mechanism for that, or should I just modify some of the source code in one >> of the cores to directly call my object? >> > > There's no hook there, as far as I know, so you'd want to modify the CPU. > Where exactly to do that depends on the CPU model. For O3 and I think > InOrder you'll also need to decide whether you want the speculative fetch PC > or the commit PC. In any of the CPUs finding where to make changes shouldn't > be too hard, and actually making the changes should be pretty easy. > > > >> FYI, originally I was planning on making my module extend the trace >> system, >> but eventually I want to build m5.fast, which I think disables tracing. >> Also, its not really a trace mechanism (I'm not dumping out any stats), >> its >> more of a control mechanism to decide when to offload exection to an >> accelerator. >> > > That makes sense. > > Gabe > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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