After looking longer at the code, I am wondering if you set the cache organization in CacheConfig.py? If so, how do you connect L2 to L3? Building on top of the example, Would it be "system.tol3bus = Bus() system.l3.cpu_side = system.tol3bus.port system.l3.mem_side = system.membus.port system.l2[i].connectMemPorts(system.tol3bus)"? The main thing that I am unsure about is system.l3.cpu_side. Does that look correct? Your help will be appreciated, thanks! Steve
On Sat, Feb 19, 2011 at 3:13 PM, Stevenson Jian <[email protected]>wrote: > Hi, > I am wondering is there any information available about what is the default > configuration between L3, L2, and L1? For example, by default does each core > have 1 L1 and 1 L2 and all L2 share the same L3? If this is not the default > configuration, how do I modify that? > Thanks, > Steve >
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