Even between a lower level cache and a higher level cache? In configs/common/Caches.py it clearly gives an example where L1 and L2 cache seem to be able to set different block sizes, so I am really confused right now. Does M5 implement exclusive or inclusive cache when it comes to a higher and a lower level cache, for example, between l1 and l2? Thanks, Steve
On Thu, Feb 24, 2011 at 2:20 AM, Gabe Black <[email protected]> wrote: > Yes, all caches have to have the same block size. I think it's for the > sake of the coherence protocol. > > Gabe > > > On 02/23/11 23:12, Stevenson Jian wrote: > > Hi, > Any comment? > I am getting assertion failures at this line. Does this line essentially > say that the lower level cache always have to have the same line size as the > higher level cache? If so, why? > Thanks! > Steve > > On Sun, Feb 20, 2011 at 10:21 PM, Stevenson Jian > <[email protected]>wrote: > >> Hi, >> Under the Cache<TagStore>::access function in cache_impl.hh, I see the >> following lines dealing with writebacks: >> if (pkt->cmd == MemCmd::Writeback) { >> assert(blkSize == pkt->getSize()); >> .... >> } >> >> If I am understanding it correctly, blkSize is the size of a line in the >> cache while pkt->getSize() stores the size of the a line in the higher cache >> that is doing a write back to the lower cache. This contradicts the assert >> statement, which essentially says that the line size of the lower cache has >> to be equal to the line size of the higher cache. Can anyone tell me where >> my understanding is wrong? >> Thanks! >> Steve >> >> > > _______________________________________________ > m5-users mailing > [email protected]http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
_______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
