Hello,
I am new to m5 and am working with the ARM_SE model, and am trying to
figure out how the registers/register file are accessed during
loads/stores with the simple timing CPU model. I need to be able to
force an error in a write to some arbitrary register which could in
theory throw off later reads/accesses. I cannot for the life of me
figure out a straightforward way to do this after looking through
src/cpu and src/cpu/simple (I want to do this in the simple timing cpu
architecture directly, not an ARM specific thing at the moment), and am
wondering if anyone could provide some suggestions.
Thanks,
Griffin Wright
The University of Michigan
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