I'm virtually certain execute() isn't called on loads or stores for the timing model, just initiateAcc and completeAcc. completeAcc isn't always called for stores in all models and so isn't really safe to use, so it's really initiateAcc and completeAcc for loads and initiateAcc for stores. The file that's generated is build/ARM_SE/arch/arm/timing_simple_cpu_exec.cc.
Gabe On 03/07/11 14:05, Korey Sewell wrote: > Look in the file "cpu/simple_thread.hh" and try running with the > traceflag "IntRegs" to get an idea of when registers are being accessed. > > The "execute()" function is called on every instruction (including > load/stores) and eventually will read the correct registers. > > The ISA description language defines what happens in that execution > and that is outputted to a file in the build directory > (build/ARM_SE/arch/timing_simple_cpu_exec.cc (?)). > > On Mon, Mar 7, 2011 at 2:45 PM, Griffin Wright <[email protected] > <mailto:[email protected]>> wrote: > > Hello, > > I am new to m5 and am working with the ARM_SE model, and am trying > to figure out how the registers/register file are accessed during > loads/stores with the simple timing CPU model. I need to be able > to force an error in a write to some arbitrary register which > could in theory throw off later reads/accesses. I cannot for the > life of me figure out a straightforward way to do this after > looking through src/cpu and src/cpu/simple (I want to do this in > the simple timing cpu architecture directly, not an ARM specific > thing at the moment), and am wondering if anyone could provide > some suggestions. > > Thanks, > Griffin Wright > The University of Michigan > _______________________________________________ > m5-users mailing list > [email protected] <mailto:[email protected]> > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > > > > -- > - Korey > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
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