Hello,
I am trying to switch back and forth between two different sets of (o3)
cpus. To do this I simply exit from the simulation every 1 million ticks
by putting exitSimLoop("exit and switch", 0); inside
TickEvent::process(). In the Simulation.py script I essentially copied
the switch functionality and put it in a loop to switch back and forth
every time the exit and switch event is seen. Here is my code to set up
the cores:
if options.big_core:
if not options.caches:
print "O3 CPU must be used with caches"
sys.exit(1)
big_core_cpus = [DerivO3CPU(defer_registration=True, cpu_id=(np+i))
for i in xrange(np)]
for i in xrange(np):
big_core_cpus[i].system = testsys
big_core_cpus[i].clock = testsys.cpu[0].clock
testsys.big_core_cpus = big_core_cpus
switch_big_core_cpu_list = [(testsys.cpu[i], big_core_cpus[i])
for i in xrange(np)]
Here is my code to do the periodic switching added just after real
simulation starts.
if options.big_core:
while exit_event.getCause() == 'exit and switch':
m5.drain(testsys)
m5.switchCpus(switch_big_core_cpu_list)
m5.resume(testsys)
exit_event = m5.simulate(maxtick - m5.curTick())
exit_cause = exit_event.getCause()
This works if I used only one core. But, if I use more than one core I
get an assertion failure:
m5.opt: build/ALPHA_FS/cpu/o3/mem_dep_unit_impl.hh:117: void
MemDepUnit<MemDepPred, Impl>::switchOut() [with MemDepPred = StoreSet,
Impl = O3CPUImpl]: Assertion `instList[0].empty()' failed.
I dumped the instruction list inside of the mem_dep_unit switchout
function and it seems as though there is a single instruction in the
list of cpu 1 for some reason. What exactly is the drain function
supposed to do? Should it drain these instructions out? Also is my
approach correct for back and forth switching?
-Tony
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