Hi,
I need to measure the average degree of MLP (memory-level parallellism)
at the L2 cache level achieved by a single core in SE mode. The L2 cache
is the last-level cache. I couldn't find any existing information on
measuring MLP in M5, so I figured I would count the amount of
outstanding L2 MSHR targets when at least one miss (i.e. MSHR) is
outstanding.
Would it be correct to simply look at the amount of MSHR targets each
time an L2 access misses and average that number? One immediate issue
with that approach is that for e.g. three successive overlapping L2
misses, the first one would "see" only a single target, when the second
comes in there would be only two, and only once the third comes in would
it see all three of them regardless of how strongly their latencies
overlap. So perhaps it would be better to sample the amount of the
outstanding MSHR targets at sufficiently small, regular intervals.
Any suggestions as to what would be the best way to go about this? I
think another option may be to look at some of the CPU internals, but
I'm much more familiar with M5's memory system.
Cheers,
Jeroen
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