I don't think we support uncachable and write combining. I can't remember if Alpha does, but we pretty much just support two memory system types. Uncachable, ordered, no-write combining and cacheable memory where writes would combine in the cache or perhaps the store buffer.
Ali On Mar 24, 2011, at 2:37 PM, Michael Levenhagen wrote: > > I'v added a hack to TLB::checkCacheability() that sets the request flags to > Request::UNCACHEABLE if the Paddr is in a given range. > My test program works though I'm not positive it's because of the hack or if > the read/writes to the memory mapped region are getting flushed from the > cache for some other reason. > > I also tried placing my device at a physical address where the > PAddrUncachedBit43 is set but this bit is lost TlbEntry. > > I guess I'm looking for a graceful solution that keeps me from changing m5 > code. At this point my change set to m5 is small and I'd like to keep that > way. > > I haven't figured out how to enable/configure Write Combining. I've search > the code and didn't find much of anything. > > Mike > > On Mar 24, 2011, at 11:31 AM, Steve Reinhardt wrote: > > >> SE mode has a page table and TLBs, so it shouldn't be too hard to put >> per-page uncacheable bits in there that are handled the same as in FS >> mode. The page table structure is defined in src/mem/page_table.*. >> At runtime it's managed via the Process class, in src/sim/process.*. >> >> Steve >> >> On Thu, Mar 24, 2011 at 10:07 AM, Michael Levenhagen <[email protected]> >> wrote: >>> Hello, >>> >>> I've incorporated parts of m5 into Sandia Lab's Structural Simulation >>> Toolkit (SST). >>> I can run a simple alpha executable in system emulation mode within SST. >>> I've also created a simple io_device and mapped it into my test apps memory >>> space. >>> >>> My question is how would I correctly set a region of physical memory to >>> UNCACHEABLE with write combining? >>> I understand that given I'm running in system emulation mode what I want to >>> do is probably not supported. >>> I'm just looking for an idea of where to start looking in the code. >>> >>> Mike >>> _______________________________________________ >>> m5-users mailing list >>> [email protected] >>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>> >> > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
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