can someone help me with this?
________________________________ From: Maya Manjrekar <[email protected]> To: [email protected] Sent: Tue, May 3, 2011 3:21:39 PM Subject: memory controller module hello, I am trying to design a memory controller module in M5. However I am unsure as to the connection and data flow. Should it connect from the L2 cache's MSHR to the DRAM? Also, can someone tell me where is the list of pending requests stored? is it in mshr.cc or somewhere else? thanks.
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