Hi Jos, There are some variables like this one that are shared all over the cpu. Although missnamed that variable is used distinguish a state update in the cpu (when a trap/fault is processed for example) from a case where some simulator function is triggering an update to architected CPU state that would cause the cpu to flush and re-execute all instructions. I don't think anyone has considered parallelizing the o3 cpu before so it's likely you would run into several of these issues.
Ali On May 6, 2011, at 9:56 AM, Ewert, Jos Kandodo wrote: > Hello, > > I am currently trying to parallelize the m5 sim ( o3/cpu.cc ) with pthreads. > In a first stage I am trying to have the various stages of the pipeline run > in parallel, ( decode.tick() fetch.tick() .... ). > Currently I have 5 pthreads each executing one of the stages. > > However ( yes you saw it comming ), > It seems to be crashing relatively randomly when cleaning up > cleanUpRemovedInsts(); and in that on: InstList.erase(removeList.front()); > because of an invalid free. > Or an assertion in the commit stage > build/ALPHA_SE/cpu/o3/commit_impl.hh:1139: bool > DefaultCommit<Impl>::commitHead(typename Impl::DynInstPtr&, unsigned int) > [with Impl = O3CPUImpl]: Assertion `!thread[tid]->inSyscall' failed. > > So I am wondering if there are some dependencies between stages that I am > unaware of . > > Greetings, > Jos Ewert > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
