Since stages communicate with each other, you'll need to be able to parallelize the communication buffers within the stages so you dont have race conditions writing/reading from certain elements and also that you preserve the timing.
The TimeBuffer struct defined in the comm.hh and used in cpu.hh (as well as the stages) is used for both forward and backward communication. A nice feature is that stages write to and read to a certain place in "time" such that you can conceivably have parallelization between stages that write (they would write to timebuffer slot X) and stages that read (reading from timebuffer slot Y). I dont think there is a easy solution for figuring out all the state variables and dependencies between stages since an out of order model can be non-trivial in some spots. A heavyweight solution to find all the dependencies might be to take all the member variables in the pipeline stages and instead declare them inside a CPU structure. (This would force say the decode stage to use the variable cpu.pipe_state.decode_status instead of just "status"). The upfront hassle of doing this might gain you the ability to see what state changes through a debugger or whatever tool you want, since you know all the state is changing in one CPU structure. Again, that's very heavweight, but outside of that just knowing how the model works (i.e. reading code, running simulations, testing), it's hard to pinpoint down every single interdependency in a out of order model. On Fri, May 6, 2011 at 10:56 AM, Ewert, Jos Kandodo < [email protected]> wrote: > Hello, > > I am currently trying to parallelize the m5 sim ( o3/cpu.cc ) with > pthreads. > In a first stage I am trying to have the various stages of the pipeline run > in parallel, ( decode.tick() fetch.tick() .... ). > Currently I have 5 pthreads each executing one of the stages. > > However ( yes you saw it comming ), > It seems to be crashing relatively randomly when cleaning up > cleanUpRemovedInsts(); and in that on: InstList.erase(removeList.front()); > because of an invalid free. > Or an assertion in the commit stage > build/ALPHA_SE/cpu/o3/commit_impl.hh:1139: bool > DefaultCommit<Impl>::commitHead(typename Impl::DynInstPtr&, unsigned int) > [with Impl = O3CPUImpl]: Assertion `!thread[tid]->inSyscall' failed. > > So I am wondering if there are some dependencies between stages that I am > unaware of . > > Greetings, > Jos Ewert > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > -- - Korey
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