On Sun, 3 Sep 2000, Christoph Egger wrote:
> To avoid mixing up DDL coming with LDDK and our DDL we are speaking about, we
> should give it a new name.
> I suggest DDL4KGI (Driver Development Language for KGI)
I'd rather say 'HDL4KGI' (Hardware Description Language) or maybe RDL
(Register Description Language) or even RBF ("Real" Bit Fields ;-).
Anyway, before finding a name, maybe you would like to have a look at the
kind of thing I'm thinking to.
Attached to this mail is a file containing a description of some VGA
registers in the fictious language I'd like to see available. This is just
a tentative syntax (do not hesitate to propose modifications) but it
should demonstrate the concept.
>From such a description, I'd expect a (to-be-written) translator to
generate C functions for easily accessing registers, so as to allow to
write "SET_Vertical_Retrace_Start(0x23);" etc. without bothering to write
carefully specific bits of the field in 2 or more registers.
I send this example because I'd like to ask a question to all the past or
future graphic chipset driver developpers that may be on the lists:
Do you think the availability of such a description language would really
ease driver development ?
Of course, my personal opinion is yes (or I would not have spoken of this
in the first place), but I'd really like to hear of different point of
views.
Thanks for your feedback,
Rodolphe
PS: Unless people on the ggi-develop mailing list are really interested, I
guess this discussion belongs to kgi-develop so, maybe future message
should not be cross-posted to both lists ?
//
// Graphic chipset registers description language
// "concept example"
//
// R. Ortalo, 2000/09/04
//
// Some direct ports
//
MISCport isa raw_port with { read := 0x3CC, write := 0x3C2 };
IOMonochrome := 0;
IOColor := 1;
VCLK0 := 0b00;
VCLK1 := 0b01;
VCLK2 := 0b10;
VCLK3 := 0b11;
// NB: '=' means true logical equality (not affectation)
MISC isa register8
with { 0 = CRTC_IO_Address in (IOMonochrome, IOColor),
1 = Enable_Display_Memory,
2-3 = Clock_Select[0-1] in (VCLK0, VCLK1, VCLK2, VCLK3),
4 in reserved,
5 = Page_Select,
6 = Horizontal_Sync_Polarity,
7 = Vertical_Sync_Polarity }
access MISCport();
// FC omitted
FEATport isa raw_port with { read := 0x3C2 };
FEAT isa register8
with { 0-3 in reserved,
4 = DAC_Sensing,
5-6 in reserved,
7 = Interrupt_Pending }
access FEATport()
read-only; // Example of read only register
// STAT, Pixel mask, Palette read, DAC state, Palette write, Pixel data
// registers omitted
//
// VGA Sequencer registers
//
SR isa indexed_port
with { read := 0x3C5, write := 0x3C5, index := 0x3C4,
max_index := 4 }; // NB: Should be overloadable (and overloaded) for SVGA
SR0 isa register8
with { 0 = Asynchronous_Reset,
1 = Synchronous_Reset,
2-7 in reserved }
access SR(0x00);
SR1 isa register8
with { 0 = 8_9_Dot_Clock,
1 in reserved,
2 = Shift_And_Load_16,
3 = Dot_Clock_2,
4 = Shift_And_Load_32,
5 = Full_Bandwidth,
6-7 in reserved }
access SR(0x01);
SR2 isa register8
with { 0-3 = Map_Enable[0-3],
4-7 in reserved }
access SR(0x02);
OFFSET_LIST := ( OFFSET_0K := 0, OFFSET_16K := 1,
OFFSET_32K := 2, OFFSET_48K := 3, OFFSET_8K := 4,
OFFSET_24K := 5, OFFSET_40K := 6, OFFSET_56K := 7 );
SR3 isa register8
with { 0-1,4 = Primary_Map_Select[0-2] in OFFSET_LIST,
2-3,5 = Secondary_Map_Select[0-2] in OFFSET_LIST,
6-7 in reserved }
access SR(0x03);
SR4 isa register8
with { 0 in reserved,
1 = Extended_Memory,
2 = Odd_Even,
3 = Chain4;
4-7 in reserved }
access SR(0x04);
// TODO: Clarify the difference between 'in' and ':=' (they are
// TODO: nearly similar except that in accepts a list and := a scalar).
//
// VGA CRTC registers
//
CR isa indexed_port
with { read := 0x3D5,
write := 0x3D5,
index := 0x3D4 };
CR0 isa register8
with { 0-7 = Horizontal_Total[0-7] }
access SR(0x0), mmio(0x00);
CR1 isa register8
with { 0-7 = Horizontal_Display_End[0-7] }
access SR(0x01), mmio(0x04);
CR2 isa register8
with { 0-7 = Horizontal_Blanking_Start[0-7] }
access SR(0x02), mmio(0x08);
CR3 isa register8
with { 0-4 = Horizontal_Blanking_End[0-4],
5-6 = Display_Enable_Skew[0-1],
7 = Compatible_Read }
access CR(0x3), mmio(0x0C);
CR4 isa register8
with { 0-7 = Horizontal_Sync_Start[0-7] }
access CR(0x4), mmio(0x10);
CR5 isa register8
with { 0-4 = Horizontal_Sync_End[0-4],
5-6 = Horizontal_Sync_Delay[0-1],
7 = Horizontal_Blanking_End[5] }
access CR(0x05), mmio(0x14);
CR6 isa register8
with { 0-7 = Vertical_Total[0-7] }
access CR(0x6), mmio(0x18);
CR7 alias CRTC_Overflow_Register
isa register8
with { 0 = Vertical_Total[8],
1 = Vertical_Display_End[8],
2 = Vertical_Retrace_Start[8],
3 = Vertical_Blanking_Start[8],
4 = Line_Compare[8],
5 = Vertical_Total[9],
6 = Vertical_Display_End[9],
7 = Vertical_Retrace_End[9] }
access CR(0x07), mmio(0x1C);
BYTEPAN_0PIXEL := 0;
BYTEPAN_8PIXELS := 1;
BYTEPAN_16PIXELS := 2;
BYTEPAN_24PIXELS := 3;
CR8 isa register8
with { 0-4 = ScreenA_Preset_Row_Scan[0-4],
5-6 = Byte_Pan[0-1] in (BYTEPAN_0PIXEL, BYTEPAN_8PIXELS,
BYTEPAN_16PIXELS, BYTEPAN_24PIXELS),
7 in reserved }
access CR(0x08), mmio(0x20);
//
// Basic types definition
//
// TODO: Refine the 'type' keyword (more precisely, make the
// TODO: distinction between layout and io).
register8 isa type with { 0-7 };
register16 isa type with { 0-15 };
register32 isa type with { 0-31 };
indexed_port isa type with { read, write, index, max_index }
value_accessor(arg in (0..$max_index)) for register8
read << io_out8($arg, $index); return io_in8($read); >>
write << io_out8($arg, $index); io_out8($value, $write) >>; // 'value' is an
implicit name
raw_port isa type with { read, write}
value_accessor() for register8
read << return io_in8($read); >>
write << io_out8($value,$write); >>;
mmio isa type
preferred value_accessor(arg) for register8
read << return mem_in8($arg + memio_buffer.baseptr); >> // TODO: How to check for
memiobuffer existence ?
write << mem_out8($value, $arg + memio_buffer.baseptr); >>
preferred value_accessor(arg) for register16
read << return mem_in16($arg + memio_buffer.baseptr); >> // TODO: idem
write << mem_out16($value, $arg + memio_buffer.baseptr); >>
preferred value_accessor(arg) for register32
read << return mem_in32($arg + memio_buffer.baseptr); >> // TODO: idem
write << mem_out32($value, $arg + memio_buffer.baseptr); >>
