Hi,
While experimenting with ghdl I found some more issues and would like to share with you..
1) Ghdl can give compilation warning when std_logic_vector more than 32 bits are passed to conv_integer, otherwise synopsys library asserts error without giving any info about file name , line no etc.
2) While simulation, I got "range check error on signal" error. I have assumed that there is some range constraint violation somewhere, please let me know if it is not the case. This error doesn't give any info about file name, line no etc, it is not possible to debug a code with this blank error.
3) Is there any way to suppress library warnings ?
e.g
"CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
Regards,
Sandeep
While experimenting with ghdl I found some more issues and would like to share with you..
1) Ghdl can give compilation warning when std_logic_vector more than 32 bits are passed to conv_integer, otherwise synopsys library asserts error without giving any info about file name , line no etc.
2) While simulation, I got "range check error on signal" error. I have assumed that there is some range constraint violation somewhere, please let me know if it is not the case. This error doesn't give any info about file name, line no etc, it is not possible to debug a code with this blank error.
3) Is there any way to suppress library warnings ?
e.g
"CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
Regards,
Sandeep
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