Hello,
i have problems with xilinx unisim libraries.
i have include them in a design file with
-------------------------------
library unisim;
use unisim.VComponents.all;
-------------------------------
I simulate with following script:
----------------------------------------------------------
export DESIGN=adder
export TB_DESIGN=adder_tb
#clear library directories if they exist
cd ../libs
if [ -e work ]; then
rm -r work
fi
if [ -e unisim ]; then
rm -r unisim
fi
#make new directories
mkdir work
mkdir unisim
cd ..
#compile xilinx unisim libraries
ghdl -i --work=unisim --workdir=libs/unisim
home/torsten/Xilinx/vhdl/src/unisims/*.vhd
#compile design files
ghdl -i --workdir=libs/work ../rtl/*.vhd
#make a design
ghdl -m -g --workdir=libs/work --warn-default-binding --warn-binding
--warn-library --warn-body --warn-specs --warn-unused ${TB_DESIGN}
echo '=================================='
echo 'design consists of following units:'
echo '----------------------------------'
ghdl -d --work=work --workdir=libs/work
echo '===================================='
echo 'detected following design hierarchy:'
echo '------------------------------------'
#run the testbench
ghdl -r ${TB_DESIGN} --disp-tree=inst --wave=waveform/${DESIGN}.ghw
echo '===================================='
#run gtkwave
gtkwave waveform/${DESIGN}.ghw
---------------------------------------------------------------------
When i compile then there is an warning
../rtl/adder.vhd:1:9: cannot find resource library "unisim"
in the Make Phase of ghdl
Is it necessary to include a path for the unisim lib in the make
commandline? and how should it look like, i have'nt found something in
the manual...
Thanx in advance
--
=======================================
= Torsten Meißner =
= Student of communication technology =
= Dresden, Germany =
= ------------------------------------=
= [EMAIL PROTECTED] =
= http://editthis.info/freefpga =
=======================================
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