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Hi I'm trying to code my first lab for my hardware
design class and we have to create an 8 bit parity generator. Using the
syntax from class, I created the following for the source:
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-- -- parity_gen.vhdl -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; entity parity_gen is port( Number : in STD_LOGIC_VECTOR(7 downto 0); Even : in std_logic; Output : out STD_LOGIC); end parity_gen; architecture one of parity_gen is
signal out1, out2, out3 : std_logic; begin Output <= number(0) xor number(1) xor number(2) xor number(3) xor number(4) xor number(5) xor number(6) xor number(7) xor EVEN; end one; and the following for the test bench
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-- -- testbench.vhdl -- ---------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; ENTITY testbench IS
END testbench; ARCHITECTURE test OF testbench IS COMPONENT parity_gen
PORT ( Number : in STD_LOGIC_VECTOR(7 downto 0); Even : in std_logic; Output : out STD_LOGIC); END COMPONENT; SIGNAL Number1 : std_logic_vector(7 DOWNTO
0);
SIGNAL Even1 : std_logic; SIGNAL Output1 : std_logic; BEGIN
part1 : parity_gen PORT MAP ( Number => Number1, Even => Even1, Output => Output1); PROCESS BEGIN FOR j IN 0 TO 255 LOOP Number1 <= conv_std_logic_vector(j, 8); Even1 <= '0'; WAIT FOR 10 ns; END LOOP; -- j FOR j IN 0 TO 255 LOOP Number1 <= conv_std_logic_vector(j, 8); Even1 <= '1'; WAIT FOR 10 ns; END LOOP; -- j END PROCESS; END test; When i try to do
'ghdl -a parity_gen.vhdl'
in the command prompt i get the following error:
parity_gen.vhd:8:10: primary unit "std_logic_signed" not found in
library "ieee"
I read up on the manual that there are some standardization issues with the
87 and 93, etc so I tried using the command listed:
'--std=87' or '--std=93'
but it seems they are not recoginized.
Any quick fixes?
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