hello all I've these two really simple files but I just can't see were
the error lives, could any one of you tell me??
I alway get "bad sum value" report.
FILE SIMPLE_XOR.VHDL
library ieee;
use ieee.std_logic_1164.all;
entity simple_xor is port (
letter_in: in std_logic;
letter_out: out std_logic
);
end simple_xor;
architecture behaviour of simple_xor is
begin
simple_xor:
letter_out <= letter_in xor '0';
end architecture behaviour;
FILE SIMPLE_XOR_TB.VHDL
library ieee;
use ieee.std_logic_1164.all;
entity simple_xor_tb is
end simple_xor_tb;
architecture behaviour of simple_xor_tb is
component simple_xor
port (
letter_in: in std_logic;
letter_out: out std_logic
);
end component;
for simple_xor_0 : simple_xor use entity work.simple_xor;
signal letter_in : std_logic;
signal letter_out: std_logic;
begin
simple_xor_0: simple_xor port map (letter_in => letter_in,
letter_out => letter_out);
process
type pattern_type is record
letter_in : std_logic;
letter_out : std_logic;
end record;
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(('0', '0'),
('1', '1'));
begin
for i in patterns'range loop
letter_in <= patterns(i).letter_in;
wait for 1 ns;
assert letter_out = patterns(i).letter_out;
report "bad sum value" severity error;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end architecture behaviour;
--
Best Regards,
Felipe Balbi
[EMAIL PROTECTED]
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