Yes, you can use XOR operator on vectors.
> I can't believe that's the only error :-p
>
> how newbie i'm with VHDL :-p
>
> ehehe..
> thanks a LOT schaeffer! :-)
>
> now, another simple question:
>
> Does VHDL know how to treat XOR operation in vectors??
>
> I mean:
> vect1 : std_logic_vector(7 downto 0);
> vect2 : std_logic_vector(7 downto 0);
> vect3 : std_logic_vector(7 downto 0)
>
> vect3 <= vect1 xor vect2;
>
> Can I use such instruction? Or should I treat each bit
separately ??
>
>
>
>
> On 4/24/07, x.schaeffer <[EMAIL PROTECTED]> wrote:
> > Hi Felipe,
> >
> > You need to remove the semicolon between your assert condition
> > and the report command, i.e.
> >
> > assert letter_out = patterns(i).letter_out
> > report "bad sum value" severity error;
> >
> > instead of
> >
> > assert letter_out = patterns(i).letter_out;
> > report "bad sum value" severity error;
> >
> > Regards,
> > Xavier
> >
> > > hello all I've these two really simple files but I just
> > can't see were
> > > the error lives, could any one of you tell me??
> > >
> > > I alway get "bad sum value" report.
> > >
> > > FILE SIMPLE_XOR.VHDL
> > > library ieee;
> > >
> > > use ieee.std_logic_1164.all;
> > >
> > > entity simple_xor is port (
> > > letter_in: in std_logic;
> > > letter_out: out std_logic
> > > );
> > > end simple_xor;
> > >
> > > architecture behaviour of simple_xor is
> > > begin
> > > simple_xor:
> > > letter_out <= letter_in xor '0';
> > > end architecture behaviour;
> > >
> > >
> > > FILE SIMPLE_XOR_TB.VHDL
> > > library ieee;
> > >
> > > use ieee.std_logic_1164.all;
> > >
> > > entity simple_xor_tb is
> > > end simple_xor_tb;
> > >
> > > architecture behaviour of simple_xor_tb is
> > >
> > > component simple_xor
> > > port (
> > > letter_in: in std_logic;
> > > letter_out: out std_logic
> > > );
> > > end component;
> > >
> > > for simple_xor_0 : simple_xor use entity
work.simple_xor;
> > > signal letter_in : std_logic;
> > > signal letter_out: std_logic;
> > >
> > > begin
> > > simple_xor_0: simple_xor port map (letter_in =>
letter_in,
> > > letter_out =>
letter_out);
> > >
> > > process
> > > type pattern_type is record
> > > letter_in : std_logic;
> > > letter_out : std_logic;
> > > end record;
> > >
> > > type pattern_array is array (natural range <>) of
> > pattern_type;
> > > constant patterns : pattern_array :=
> > > (('0', '0'),
> > > ('1', '1'));
> > > begin
> > > for i in patterns'range loop
> > > letter_in <= patterns(i).letter_in;
> > > wait for 1 ns;
> > >
> > > assert letter_out = patterns(i).letter_out;
> > > report "bad sum value" severity error;
> > > end loop;
> > > assert false report "end of test" severity
note;
> > > wait;
> > >
> > > end process;
> > > end architecture behaviour;
> > >
> > >
> > >
> > >
> > >
> > > --
> > > Best Regards,
> > >
> > > Felipe Balbi
> > > [EMAIL PROTECTED]
> > >
> > > _______________________________________________
> > > Ghdl-discuss mailing list
> > > [email protected]
> > > https://mail.gna.org/listinfo/ghdl-discuss
> > >
> >
> > Créez votre adresse électronique [EMAIL PROTECTED]
> > 1 Go d'espace de stockage, anti-spam et anti-virus intégrés.
> >
> >
> > _______________________________________________
> > Ghdl-discuss mailing list
> > [email protected]
> > https://mail.gna.org/listinfo/ghdl-discuss
> >
>
>
> --
> Best Regards,
>
> Felipe Balbi
> [EMAIL PROTECTED]
>
> _______________________________________________
> Ghdl-discuss mailing list
> [email protected]
> https://mail.gna.org/listinfo/ghdl-discuss
>
Créez votre adresse électronique [EMAIL PROTECTED]
1 Go d'espace de stockage, anti-spam et anti-virus intégrés.
_______________________________________________
Ghdl-discuss mailing list
[email protected]
https://mail.gna.org/listinfo/ghdl-discuss
