Hello,
I have a strange bug in specific code, for more detail read the source
in attachement.
also in attachement: Makefile, output from ghdl(wrong) and output from
modelsim(right)
Can you confirm the bug ?
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
entity bug is
end entity;
architecture testbench of bug is
--Definition of Architecture adapted custom types
subtype column is std_logic_vector(31 downto 0);
type matrix is array (natural range <>) of column;
--clock
signal clk:std_logic:='0';
begin
--generate 1 rising edge clock
clk<='1' after 10 ns;
aes_core:process(clk)
--##############DEBUG MATRIX OUTPUT FUNCTION##################
procedure debugState(data:matrix;info:string)is
variable ligne:line;
variable i,j:natural;
begin
write(ligne,info & " =");
writeline(output,ligne);
for i in 0 to 3 loop
write(ligne,string'(" | "));
for j in 3 downto 0 loop
hwrite(ligne,data(j)((i+1)*8-1 downto i*8));
write(ligne,string'(" "));
end loop;
write(ligne,string'("|"));
writeline(output,ligne);
end loop;
write(ligne,string'(""));
writeline(output,ligne);
end debugState;
--##########################################################
variable next_state_column:column:=x"F0F1F2F3";
variable state,state2,state3:matrix(3 downto 0);
begin
if rising_edge(clk) then
--- initialisation state=state2=state3
state:=(x"44434241",x"34333231",x"24232221",x"14131211");
state2:=state;
state3:=state;
--- making sure that state=state2=state3 via plotting
debugState(state,"State");
debugState(state,"State2");
debugState(state,"State3");
--- shifting right by 1 column and inserting a new column on the left using 3 different coding style
for i in 0 to 2 loop
state(i):=state(i+1);
end loop;
state(state'left):=next_state_column;
state2:=next_state_column & state2(3 downto 1);
state3(2 downto 0):=state3(3 downto 1);
state3(3):=next_state_column;
-------------------------------------
--- plotting output: method 2 and 3 give bad result
debugState(state,"State after fifo insertion");
debugState(state2,"State2 after fifo insertion");
debugState(state2,"State3 after fifo insertion");
--assert state2=state report "erreur" severity failure;
--assert state3=state report "erreur" severity failure;
end if;
end process;
end architecture;
State =
| 41 31 21 11 |
| 42 32 22 12 |
| 43 33 23 13 |
| 44 34 24 14 |
State2 =
| 41 31 21 11 |
| 42 32 22 12 |
| 43 33 23 13 |
| 44 34 24 14 |
State3 =
| 41 31 21 11 |
| 42 32 22 12 |
| 43 33 23 13 |
| 44 34 24 14 |
State after fifo insertion =
| F3 41 31 21 |
| F2 42 32 22 |
| F1 43 33 23 |
| F0 44 34 24 |
State2 after fifo insertion =
| 00 41 31 21 |
| 00 42 32 22 |
| 00 43 33 23 |
| 00 44 34 24 |
State3 after fifo insertion =
| 00 41 31 21 |
| 00 42 32 22 |
| 00 43 33 23 |
| 00 44 34 24 |
run
# State =
# | 41 31 21 11 |
# | 42 32 22 12 |
# | 43 33 23 13 |
# | 44 34 24 14 |
#
# State2 =
# | 41 31 21 11 |
# | 42 32 22 12 |
# | 43 33 23 13 |
# | 44 34 24 14 |
#
# State3 =
# | 41 31 21 11 |
# | 42 32 22 12 |
# | 43 33 23 13 |
# | 44 34 24 14 |
#
# State after fifo insertion =
# | F3 41 31 21 |
# | F2 42 32 22 |
# | F1 43 33 23 |
# | F0 44 34 24 |
#
# State2 after fifo insertion =
# | F3 41 31 21 |
# | F2 42 32 22 |
# | F1 43 33 23 |
# | F0 44 34 24 |
#
# State3 after fifo insertion =
# | F3 41 31 21 |
# | F2 42 32 22 |
# | F1 43 33 23 |
# | F0 44 34 24 |
#
bug: bug.vhd
ghdl -a --ieee=synopsys bug.vhd
ghdl -e --ieee=synopsys bug
./bug --vcd=bug.vcd --stop-time=1500ns
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