Ian Chapman wrote: > Is this a ghdl error or simply a case of what they can pack into a cpld? >
Neither. It's working VHDL code. The code however doesn't follow the RTL synthesis conventions from P1076.6, which wants an elsif for the clock event following an asynchronous reset. Note that only the clock and the reset are required in the sensitivity list for the counter as Kendrick's version with the elsif shows. He moved the rx_br_ctr5 assignment a concurrent signal assignment statement outside the process. The tools for synthesizing a CPLD may have limitations based on CPLD complexity, but should have complained in a different fashion. I'd expect the mux for the counter incrementer and reloading by rx_start_pul to give you heartburn with simple devices. Note that on the first clock event following PG going to a '1', the counter is guaranteed to be set to zero following comparison to define_rx_baude_rate, because PG sets it to define_rx_baude_rate. Getting the counter to zero can also be done by a synchronous reset with rx_start_pul = '1'. One of these seems redundant. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
