Hi all,
This bit of code was assembled, elaborated and run quite well
with ghdl generating good results on gtkwave using Linux. When I ran it on
XP both Xilinx and lattice it gave errors bad synchronous description.
Comparing it with the example I should have the
if rising edge etc as
elsif rising edge.etc
Is this a ghdl error or simply a case of what they can pack into a cpld?
Regards Ian.
RX_BR_counter:process (OSC_10MHz, PG, rx_start_pul, rx_br_ctr_int,
rx_clk_int, br_start_pul)
begin
if PG = '0' then
rx_br_ctr_int <= define_rx_baude_rate;
end if;
if rising_edge (OSC_10MHz) then
if rx_start_pul = '1' or rx_br_ctr_int = define_rx_baude_rate
then
rx_br_ctr_int <= (others => '0');
else
rx_br_ctr_int <= rx_br_ctr_int + 1;
end if;
end if;
rx_br_ctr5 <= std_logic (rx_br_ctr_int(5));
end process;
Lattice error
# Error: [46237]: "c:/vsn4_pulsar/ghdl/rx/rx.vhd", line 69: Unsupported
Clocking style: Signal/Variable rx_br_ctr_int is assigned in async part
before sync part ...
# Error: [46292]: Module work.UART_RX(behavioral) cannot be compiled because
it contains non-rtl constructs. Please check the log for warnings or errors
about non-synthesizable constructs in this module. # Error: [46237]:
"c:/vsn4_pulsar/ghdl/rx/rx.vhd", line 69: Unsupported Clocking style:
Signal/Variable rx_br_ctr_int is assigned in async part before sync part ...
# Error: [46292]: Module work.UART_RX(behavioral) cannot be compiled because
it contains non-rtl constructs. Please check the log for warnings or errors
about non-synthesizable constructs in this module.
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