Quoting Jason Pyeron <[EMAIL PROTECTED]>: > I thought that if the delta cycles do not change anything then the simulation > would exit? > > I stripped the test down to a simple test case and did a trace.
No, there is no such a rule. It is perfectly legal to have a VHDL program/design without signals. Tristan. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
